0700 // This file contains definitions for the
0701 // x86 memory management unit (MMU).
0702 
0703 // Eflags register
0704 #define FL_CF           0x00000001      // Carry Flag
0705 #define FL_PF           0x00000004      // Parity Flag
0706 #define FL_AF           0x00000010      // Auxiliary carry Flag
0707 #define FL_ZF           0x00000040      // Zero Flag
0708 #define FL_SF           0x00000080      // Sign Flag
0709 #define FL_TF           0x00000100      // Trap Flag
0710 #define FL_IF           0x00000200      // Interrupt Enable
0711 #define FL_DF           0x00000400      // Direction Flag
0712 #define FL_OF           0x00000800      // Overflow Flag
0713 #define FL_IOPL_MASK    0x00003000      // I/O Privilege Level bitmask
0714 #define FL_IOPL_0       0x00000000      //   IOPL == 0
0715 #define FL_IOPL_1       0x00001000      //   IOPL == 1
0716 #define FL_IOPL_2       0x00002000      //   IOPL == 2
0717 #define FL_IOPL_3       0x00003000      //   IOPL == 3
0718 #define FL_NT           0x00004000      // Nested Task
0719 #define FL_RF           0x00010000      // Resume Flag
0720 #define FL_VM           0x00020000      // Virtual 8086 mode
0721 #define FL_AC           0x00040000      // Alignment Check
0722 #define FL_VIF          0x00080000      // Virtual Interrupt Flag
0723 #define FL_VIP          0x00100000      // Virtual Interrupt Pending
0724 #define FL_ID           0x00200000      // ID flag
0725 
0726 // Control Register flags
0727 #define CR0_PE		0x00000001	// Protection Enable
0728 #define CR0_MP		0x00000002	// Monitor coProcessor
0729 #define CR0_EM		0x00000004	// Emulation
0730 #define CR0_TS		0x00000008	// Task Switched
0731 #define CR0_ET		0x00000010	// Extension Type
0732 #define CR0_NE		0x00000020	// Numeric Errror
0733 #define CR0_WP		0x00010000	// Write Protect
0734 #define CR0_AM		0x00040000	// Alignment Mask
0735 #define CR0_NW		0x20000000	// Not Writethrough
0736 #define CR0_CD		0x40000000	// Cache Disable
0737 #define CR0_PG		0x80000000	// Paging
0738 
0739 // Segment Descriptor
0740 struct segdesc {
0741   uint lim_15_0 : 16;  // Low bits of segment limit
0742   uint base_15_0 : 16; // Low bits of segment base address
0743   uint base_23_16 : 8; // Middle bits of segment base address
0744   uint type : 4;       // Segment type (see STS_ constants)
0745   uint s : 1;          // 0 = system, 1 = application
0746   uint dpl : 2;        // Descriptor Privilege Level
0747   uint p : 1;          // Present
0748   uint lim_19_16 : 4;  // High bits of segment limit
0749   uint avl : 1;        // Unused (available for software use)
0750   uint rsv1 : 1;       // Reserved
0751   uint db : 1;         // 0 = 16-bit segment, 1 = 32-bit segment
0752   uint g : 1;          // Granularity: limit scaled by 4K when set
0753   uint base_31_24 : 8; // High bits of segment base address
0754 };
0755 
0756 // Normal segment
0757 #define SEG(type, base, lim, dpl) (struct segdesc)    \
0758 { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff,      \
0759   ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1,       \
0760   (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 }
0761 #define SEG16(type, base, lim, dpl) (struct segdesc)  \
0762 { (lim) & 0xffff, (uint)(base) & 0xffff,              \
0763   ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1,       \
0764   (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 }
0765 
0766 #define DPL_USER    0x3     // User DPL
0767 
0768 // Application segment type bits
0769 #define STA_X       0x8     // Executable segment
0770 #define STA_E       0x4     // Expand down (non-executable segments)
0771 #define STA_C       0x4     // Conforming code segment (executable only)
0772 #define STA_W       0x2     // Writeable (non-executable segments)
0773 #define STA_R       0x2     // Readable (executable segments)
0774 #define STA_A       0x1     // Accessed
0775 
0776 // System segment type bits
0777 #define STS_T16A    0x1     // Available 16-bit TSS
0778 #define STS_LDT     0x2     // Local Descriptor Table
0779 #define STS_T16B    0x3     // Busy 16-bit TSS
0780 #define STS_CG16    0x4     // 16-bit Call Gate
0781 #define STS_TG      0x5     // Task Gate / Coum Transmitions
0782 #define STS_IG16    0x6     // 16-bit Interrupt Gate
0783 #define STS_TG16    0x7     // 16-bit Trap Gate
0784 #define STS_T32A    0x9     // Available 32-bit TSS
0785 #define STS_T32B    0xB     // Busy 32-bit TSS
0786 #define STS_CG32    0xC     // 32-bit Call Gate
0787 #define STS_IG32    0xE     // 32-bit Interrupt Gate
0788 #define STS_TG32    0xF     // 32-bit Trap Gate
0789 
0790 // A linear address 'la' has a three-part structure as follows:
0791 //
0792 // +--------10------+-------10-------+---------12----------+
0793 // | Page Directory |   Page Table   | Offset within Page  |
0794 // |      Index     |      Index     |                     |
0795 // +----------------+----------------+---------------------+
0796 //  \--- PDX(la) --/ \--- PTX(la) --/
0797 
0798 // page directory index
0799 #define PDX(la)		((((uint) (la)) >> PDXSHIFT) & 0x3FF)
0800 // page table index
0801 #define PTX(la)		((((uint) (la)) >> PTXSHIFT) & 0x3FF)
0802 
0803 // construct linear address from indexes and offset
0804 #define PGADDR(d, t, o)	((uint) ((d) << PDXSHIFT | (t) << PTXSHIFT | (o)))
0805 
0806 // turn a kernel linear address into a physical address.
0807 // all of the kernel data structures have linear and
0808 // physical addresses that are equal.
0809 #define PADDR(a)       ((uint) a)
0810 
0811 // Page directory and page table constants.
0812 #define NPDENTRIES	1024		// page directory entries per page directory
0813 #define NPTENTRIES	1024		// page table entries per page table
0814 
0815 #define PGSIZE		4096		// bytes mapped by a page
0816 #define PGSHIFT		12		// log2(PGSIZE)
0817 
0818 #define PTXSHIFT	12		// offset of PTX in a linear address
0819 #define PDXSHIFT	22		// offset of PDX in a linear address
0820 
0821 #define PGROUNDUP(sz)  (((sz)+PGSIZE-1) & ~(PGSIZE-1))
0822 #define PGROUNDDOWN(a) ((char*)((((unsigned int)(a)) & ~(PGSIZE-1))))
0823 
0824 // Page table/directory entry flags.
0825 #define PTE_P		0x001	// Present
0826 #define PTE_W		0x002	// Writeable
0827 #define PTE_U		0x004	// User
0828 #define PTE_PWT		0x008	// Write-Through
0829 #define PTE_PCD		0x010	// Cache-Disable
0830 #define PTE_A		0x020	// Accessed
0831 #define PTE_D		0x040	// Dirty
0832 #define PTE_PS		0x080	// Page Size
0833 #define PTE_MBZ		0x180	// Bits must be zero
0834 
0835 // Address in page table or page directory entry
0836 #define PTE_ADDR(pte)	((uint) (pte) & ~0xFFF)
0837 
0838 typedef uint pte_t;
0839 
0840 // Task state segment format
0841 struct taskstate {
0842   uint link;         // Old ts selector
0843   uint esp0;         // Stack pointers and segment selectors
0844   ushort ss0;        //   after an increase in privilege level
0845   ushort padding1;
0846   uint *esp1;
0847   ushort ss1;
0848   ushort padding2;
0849   uint *esp2;
0850   ushort ss2;
0851   ushort padding3;
0852   void *cr3;         // Page directory base
0853   uint *eip;         // Saved state from last task switch
0854   uint eflags;
0855   uint eax;          // More saved state (registers)
0856   uint ecx;
0857   uint edx;
0858   uint ebx;
0859   uint *esp;
0860   uint *ebp;
0861   uint esi;
0862   uint edi;
0863   ushort es;         // Even more saved state (segment selectors)
0864   ushort padding4;
0865   ushort cs;
0866   ushort padding5;
0867   ushort ss;
0868   ushort padding6;
0869   ushort ds;
0870   ushort padding7;
0871   ushort fs;
0872   ushort padding8;
0873   ushort gs;
0874   ushort padding9;
0875   ushort ldt;
0876   ushort padding10;
0877   ushort t;          // Trap on task switch
0878   ushort iomb;       // I/O map base address
0879 };
0880 
0881 // Gate descriptors for interrupts and traps
0882 struct gatedesc {
0883   uint off_15_0 : 16;   // low 16 bits of offset in segment
0884   uint cs : 16;         // code segment selector
0885   uint args : 5;        // # args, 0 for interrupt/trap gates
0886   uint rsv1 : 3;        // reserved(should be zero I guess)
0887   uint type : 4;        // type(STS_{TG,IG32,TG32})
0888   uint s : 1;           // must be 0 (system)
0889   uint dpl : 2;         // descriptor(meaning new) privilege level
0890   uint p : 1;           // Present
0891   uint off_31_16 : 16;  // high bits of offset in segment
0892 };
0893 
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0899 
0900 // Set up a normal interrupt/trap gate descriptor.
0901 // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate.
0902 //   interrupt gate clears FL_IF, trap gate leaves FL_IF alone
0903 // - sel: Code segment selector for interrupt/trap handler
0904 // - off: Offset in code segment for interrupt/trap handler
0905 // - dpl: Descriptor Privilege Level -
0906 //        the privilege level required for software to invoke
0907 //        this interrupt/trap gate explicitly using an int instruction.
0908 #define SETGATE(gate, istrap, sel, off, d)                \
0909 {                                                         \
0910   (gate).off_15_0 = (uint) (off) & 0xffff;                \
0911   (gate).cs = (sel);                                      \
0912   (gate).args = 0;                                        \
0913   (gate).rsv1 = 0;                                        \
0914   (gate).type = (istrap) ? STS_TG32 : STS_IG32;           \
0915   (gate).s = 0;                                           \
0916   (gate).dpl = (d);                                       \
0917   (gate).p = 1;                                           \
0918   (gate).off_31_16 = (uint) (off) >> 16;                  \
0919 }
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